1. Technical Field
The present disclosure relates to a panel formed of an array of liquid crystal cells for use in a nanoprojector.
2. Discussion of the Related Art
FIG. 1 schematically shows a panel used in a nanoprojector to project an image.
Panel 1 comprises an array of cells 3, which is shown in enlarged fashion 5 in FIG. 1. Each cell comprises a liquid crystal layer 7 housed between upper and lower transparent electrodes, not shown in FIG. 1. Each cell further comprises a MOS control transistor 9 arranged above the upper electrode. Transistors 9 are connected to row decoders 11 and to column decoders 13. Panel 1 further comprises drive circuits 15 enabling to synchronize the cell switching-on.
The light emitted by a light source 17 crosses panel 1 and an image is projected on a screen (not shown).
FIG. 2 is an electric diagram illustrating the operation of a panel of the type illustrated in FIG. 1.
For each cell 3, liquid crystal layer 7 between the upper and lower transparent electrodes forms a capacitance 21. The upper electrode of capacitance 21 is connected to a main electrode of MOS control transistor 9 of the cell. Transistor 9 enables to control the optical attenuation level of the cell.
The gate of each MOS control transistor 9 is connected to a row 23. The source of each transistor 9 is connected to a column 25. The grey levels corresponding to the image to be projected are transmitted to each cell by an electric voltage value sent onto each column 25. These values are transmitted row by row to control transistors 9.
Capacitance 21 of each liquid crystal cell has a low value, for example, on the order of a few fF. Leakage currents at the transistor level cause signal losses between two image refreshment operations. A storage capacitance 27 is thus provided and arranged in parallel with capacitance 21 to store the image data for a sufficiently long time.
FIG. 3 is a cross-section view schematically showing a portion of a panel of the type illustrated in FIG. 1. Dotted lines 31 delimit cells 3.
Each cell 3 comprises a liquid crystal layer 7 between a lower transparent electrode 33 and an upper transparent electrode 35. Lower transparent electrode 33 is laid on a transparent plate 32. Lower transparent electrode 33 continuously extends under liquid crystal layer 7 and is common to all cells 3, while an upper transparent electrode 35 is associated with each cell 3. Upper electrodes 35 are arranged at a distance from one another to avoid short-circuiting the cells.
A silicon oxide layer 37 covered with a layer 39 is arranged above upper electrodes 35. As will be seen hereafter in the context of a panel manufacturing embodiment, layers 37 and 39 respectively correspond to the buried oxide layer, currently called BOX (“Buried OXide”), and to the active layer of a substrate of silicon-on-insulator type (SOI).
For each cell 3, a MOS control transistor 9 has been formed in a silicon layer 40 of layer 39, the rest, 41, of layer 39 having been oxidized. It should be noted that regions 41 are transparent. Each MOS transistor 9 comprises a gate 42 extending on silicon area 40 and insulated therefrom by a gate insulator 43. Spacers 45 are present on both sides of gate 42. Source and drain 47 extend in silicon area 40 on either side of gate 42.
Regions 41 of layer 39 and MOS transistors 9 have been covered with an insulating layer 51, itself covered with metallization levels 53 separated by insulating layers. There, for example, are six metallization levels 53, designated with reference numerals 55 to 60. A transparent plate 54 covers the structure.
For each cell 3, a via 61 of a conductive material connects a metallization of lower metallization level 55, connected to a main electrode of MOS control transistor 9, to upper electrode 35.
Generally, lower metallization level 55 and intermediary metallization level 56 are used to form the source, drain, and gate contact connections of control transistors 9. Upper metallization level 60 is used to power the cells.
For each cell, upper metallization level 60 extends above control transistor 9 and is used as an optical screen to protect transistors 9 from light rays.
In the case of a cell comprising six metallization levels, there remain at least two metallization levels, for example, intermediate levels 57, 58, 59, which may be used to form a MIM (Metal Insulator Metal) capacitance integrated above the MOS control transistor, such a MIM capacitance forming storage capacitance 27 of the cell.
Further, the useful surface area of each cell corresponds to the cell surface area which is capable of being crossed by light rays, which excludes the surface area taken up by transistors.
When a panel of the type illustrated in FIG. 3 is used in a nanoprojector, a very intense light flow reaches the panel surface, on the side of the MOS control transistors.
A disadvantage of such a panel is that, despite the presence of the upper metallization level intended to block light rays directly reaching the control transistors, the operation of the control transistors is disturbed by parasitic radiations. As a result, the MOS control transistors have high leakage currents.
Another disadvantage of such a panel is the need to form at least from five to six metallization levels above the control transistors to be able to integrate the storage capacitance of each cell above the control transistors, in the metallization levels.
Currently, to decrease the manufacturing cost of panels intended to be used in a nanoprojector, the number of metallization levels formed above the control transistors has to be decreased. In the case where less than five metallization levels are desired to be formed, for example, only three metallization levels, the cell storage capacitance cannot be integrated above the control transistors, the metallization levels being all used to form the source, drain, and gate contact connections of the control transistors and to power the cells. For each cell, the storage capacitance is then formed next to the MOS control transistor, for example, in the form of a MOS capacitance. The useful surface area of each panel is then decreased.
There thus is a need for a panel formed of an array of liquid crystal cells intended to be used in a nanoprojector which overcomes at least some of the disadvantages of the above-described panels.